Some applications require the integration of digital to analog converter and/or analog to digital converter together with digital circuits. Digital circuits consume less power and required less area in fine line CMOS process, i.e. processes below 100 nm. In many cases the choice of process technology is dictated by the constraints of the digital circuitry.
However, analog and mixed signals circuits, like DACs and ADCs, suffer from the poor matching performance and the low power supply voltages of fine line CMOS processes. Applying conventional DAC/ADC design techniques in fine line CMOS processes result in inefficient designs.
In the case of current steering DAC architectures the analog output is represented by the sum of unit segment currents. The unit segment currents are steered either to the positive or to the negative output of the DAC. The steering is achieved by switching elements that are controlled by signals derived from the DAC input signal. The matching of these unit segments determines the performance of the DAC. Performance parameters such as, integral non linearity (INL), differential non linearity (DNL) and spurious free dynamic range (SFDR) are affected. One method to calibrate a DAC is to equalize all the unit segments. With this method the unit segments are compared to a reference segment. Trim currents are added or subtracted to the unit segment currents such that their value is close to the reference segment currents. This can be done in a background mode or in dedicated calibration cycle during which the DAC is not producing an output signal. Another approach is digital pre distortion (DPD). With DPD, the unit segments are measured and new input codes for the DAC are calculated based on the measured values of the unit segments.